In general, a switching regulator has better power conversion efficiency, while an LDO circuit provides lower noise in its output. Therefore, as shown in FIG. 1, a power supply combining both has been proposed which first converts an input voltage Vin to an intermediate voltage Vm, and next converts the intermediate voltage Vm to an output voltage Vout. The switching regulator (SR) 10 provides a first stage high-efficiency conversion, while the LDO circuit (LDO) 20 filters the ripple noise in the intermediate voltage Vm. Naturally, in this arrangement, the intermediate voltage Vm is conventionally designed to be as close to the output voltage Vout as possible, so that most power conversion is achieved in the first stage switching regulator, for better power conversion efficiency.
The capability of an LDO circuit to filter the ripple noise is referred to as the “power supply rejection ratio”, PSRR. PSRR is relevant to three factors: the voltage drop from an input of an LDO circuit to its output (referred to as the “dropout voltage” in this invention); the load current at its output; and the quiescent current of the LDO circuit. The higher the dropout voltage, the better the PSRR; the higher the load current, the worse the PSRR; the higher the quiescent current, the better the PSRR. However, apparently, to increase the dropout voltage or the quiescent current will decrease the power conversion efficiency.
Conventionally, there is no “adaptive” design in this kind of power supply, namely to vary the power conversion ratios of the two stages according to the load condition all prior art circuits follow a simple logic: to set the voltage drop between the intermediate voltage Vm and the output voltage Vout to a constant as low as possible, that is, to set the output of the first stage switching regulator to a fixed voltage as close to the output voltage Vout as possible. The corresponding circuit is simple, and has high power conversion efficiency, but if the load circuit receiving the supplied power is sensitive to noises, such prior art circuits can not meet the expectation required by the load circuit.
More specifically, referring to schematic diagram of FIG. 2 wherein the horizontal coordinate is the load current and the vertical coordinate is the magnitude, it can be seen that as the load current (output current) increases, the noise in the intermediate voltage Vm also increases, and the PSRR of the LDO circuit decreases. The overall effect is shown by the third curve, that the overall noise of the output voltage Vout increases along with the increase of the load current.
In view of the above, it is desired to provide a power supply capable of dynamically controlling the power conversion efficiency and the overall noise, so that they are balanced at an optimum according to the requirement from the load circuit.